SV51006
2014.01.10
Programmable Output Slew-Rate Control
5-19
Programmable Output Slew-Rate Control
The programmable output slew-rate control in the output buffer of each regular- and dual-function I/O pin
allows you to configure the following:
? Fast slew-rate — provides high-speed transitions for high-performance systems. Fast slew rates improve
the available timing margin in memory-interface applications or when the output pin has high-capacitive
loading.
? Slow slew-rate — reduces system noise and crosstalk but adds a nominal delay to the rising and falling
edges.
You can specify the slew-rate on a pin-by-pin basis because each I/O pin contains a slew-rate control.
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate
setting for your specific application.
Related Information
Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, or increase
clock-to-output times. This feature helps read and write timing margins because it minimizes the
uncertainties between signals in the bus.
Each single-ended and differential I/O pin can have a different input delay from pin-to-input register or a
delay from output register-to-output pin values to ensure that the signals within a bus have the same delay
going into or out of the device.
For more information about the programmable IOE delay specifications, refer to the device datasheet.
Related Information
? Programmable IOE Features in Stratix V Devices on page 5-17
Programmable Output Buffer Delay
The delay chains are built inside the single-ended output buffer. There are four levels of output buffer delay
settings. By default, there is no delay.
The delay chains can independently control the rising and falling edge delays of the output buffer, allowing
you to:
?
?
?
?
Adjust the output-buffer duty cycle
Compensate channel-to-channel skew
Reduce simultaneous switching output (SSO) noise by deliberately introducing channel-to-channel skew
Improve high-speed memory-interface timing margins
For more information about the programmable output buffer delay specifications, refer to the device datasheet.
I/O Features in Stratix V Devices
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Altera Corporation
相关PDF资料
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